High speed data communications channels typically lock onto a phase of a received data stream. The receiving device typically includes a phase-lock loop (PLL) circuit that locks onto the phase of the received data stream. For example, radio frequency (RF) communications channels are established by wireless communications devices in a wireless network.
Referring now to FIG. 1, an exemplary PLL 10 includes a phase detector (PD) 12, a charge pump 14, a loop filter 16, a voltage controlled oscillator (VCO) 18, and a frequency divider 20. The VCO 18 generates an output signal that is divided by the frequency divider 20 and fed back to the PD 12. The PD 12 detects a phase difference between a reference frequency signal 22 (such as the received data stream) and the feedback or divided output signal 24. The PD 12 generates one or more phase difference signals 26, for example signals 30 and 32, that drive the charge pump 14, as will be described below.
The charge pump 14 receives the phase difference signals 26 and generates an output signal that is used to adjust the output of the VCO 18. The output signal may be a pulse width modulated current signal. Performance of the charge pump 14 is typically characterized by switching speed and phase offset. Phase offset refers to the voltage generated by the charge pump 14 when the phase of the reference signal 22 and the feedback signal 24 are the same. Ideally the phase offset of the charge pump 14 is zero.
The output of the charge pump 14 is filtered by the optional loop filter 16. The loop filter 16 may include a capacitor-based integrating circuit, although other types of filters may be used. The desired frequency for the output signal 28 of the VCO 18 may be different than the frequency of the reference signal 22. The frequency divider 20 adjusts the frequency of the output signal 28 based on the ratio of the desired output frequency to the reference frequency.
In some approaches, the phase difference signals 30 and 32 that are generated by the PD 12 are UP and DOWN signals, respectively. UP signals indicate positive differences between the reference signal and the output signal and DOWN signals represent negative differences. Additional details can be found in “Voltage Controlled Oscillator Formed of Two Differential Transconductors”, U.S. Pat. No. 5,635,879, to Sutardja et al., which is commonly assigned and which is hereby incorporated by reference in its entirety.
Referring now to FIG. 2, one exemplary charge pump 14 includes a first current source 40 and a second current source 42. One end of the first current source 40 is connected to a first power supply 44 or Vdd and an opposite end is connected to transistors 46 and 48. The transistor 46 selectively connects the first current source 40 to a reference node 50. The transistor 48 selectively connects the first current source 40 to an output node 52. The UP signal is applied to an inverter 70, which has an output that communicates with a gate 84 of the transistor 46. An inverted UP signal is applied to an inverter 72, which has an output that communicates with a gate 86 of the transistor 48.
A transistor 58 selectively connects the second current source 42 to the reference node 50. A transistor 60 selectively connects the second current source 42 to the output node 52. An inverted DOWN signal is applied to an inverter 74, which has an output that communicates with a gate 88 of the transistor 58. The DOWN signal is applied to an inverter 76, which has an output that communicates with a gate 90 of the transistor 60. The transistors 46 and 48 are switched in response to the UP and inverted UP signals. The transistors 58 and 60 are switched in response to the DOWN and the inverted DOWN signals. Typically, the inverters 70, 72, 74, and 76 are biased between ground 80 and a supply voltage 82. In this circuit, the gates 84, 86, 88, and 90 are switched from rail to rail, which tends to increase charge injection and phase offset.
An alternative embodiment for driving a charge pump circuit is shown in FIG. 3. Inverters 100, 102, 104, and 106 are biased between a fixed low voltage 108 and a fixed high voltage 110 rather than between supply voltage and ground. For example, the inverters 100, 102, 104, and 106 may be biased by a fixed low voltage such as 1.0 volt and a fixed high voltage such as 1.5 volts for a voltage swing of 0.5 volts.
The circuit arrangement in FIG. 3 reduces charge injection. However, the inverters 100, 102, 104, and 106 do not receive the full range of the voltage supply, which reduces the switching speed of transistors 46, 48, 58, and 60. The switching speed is reduced because the PMOS transistors 46 and 48 do not have sufficient overdrive voltage to quickly charge the gate when switching to Vhigh. Likewise, the NMOS transistors 58 and 60 typically do not have sufficient overdrive voltage to quickly discharge the gate to switch to Vlow.